1. Field of the Invention
The present invention relates to a method for manufacturing a printed circuit board adapted to flip-chip packaging of LSI, and the like, more particularly to a method for manufacturing a printed circuit board enabling high density wiring.
2. Description of the Related Art
In the case of a known method for manufacturing a printed circuit board, a dimensional correction amount of a wiring pattern layer formed on a conductive layer is obtained on the basis of an alignment via hole, and an outer pattern layer is formed using the dimensional correction amount, as described in Japanese Unexamined Patent Application Publication No. 2000-223833 (page. 1).
There is a known pattern-forming method that includes a measurement process in which a distance between marks on a substrate is measured and stored as a measurement data, and an image data calculation process in which an image data for a new image position is calculated on the basis of the measurement data, as described in Japanese Unexamined Patent Application Publication No. 2004-272167 (page. 3).
There is also a known method for manufacturing a printed circuit board in which arbitrary pattern positions or arbitrary reference positions of an inner core substrate are measured and corrected dimensions are determined by calculating the difference between the measurement results and reference values therefor, and a via hole in an outer layer substrate composed of prepreg material is formed on the basis of the data corresponding to the correction dimensions, as described in Japanese Unexamined Patent Application Publication No. 2002-223078 (page. 2).
Moreover, there is a known method for manufacturing a printed circuit board in which position coordinates of an LSI mounted area and target marks are calculated on the basis of image data obtained by photographing the target marks, correction amounts (rotation angle and parallel displacement) needed for alignment are determined by calculating the difference between the calculated position coordinates and designed position coordinates corresponding to target marks for aligning respective LSI mounted areas and a thin layer pattern, and exposure data needed for exposing the thin layer pattern are transformed on the basis of the correction amounts, as described in Japanese Unexamined Patent Application Publication No. H10-186683 (page. 2).
Incidentally, an imaging device is known that is capable to perform an appropriate scaling correction treatment against a dimensional variance of each of objects to be imaged, and is also capable to image a pattern with high precision regardless of dimensional variances of the objects to be imaged by performing the scaling correction treatment in a unit of a pixel or less of raster data, as described in Japanese Unexamined Patent Application Publication No. H9-323180 (page. 1 and 18).
Electronic products have been required to be compact and still be multifunctional, and such requirements are expected to increase also in coming years, which brings about a demand for a high degree of integration and miniaturization of a printed wiring board. An effective way to respond to the need is to achieve a high-density wiring, in which a pitch between adjacent pattern lines is made fine.
However, since a printed wiring board is subjected to a plating treatment in the manufacturing process, it is considerably deformed as a whole due to expansion/contraction of a resin layer constituting a substrate. It is therefore necessary to form a via land provided in each of upper and lower wiring layers in advance so as to have a diameter size larger than the diameter size of a via hole provided in an insulation layer between the upper and lower wiring layers. Otherwise, bonding of the via lands and a conductive portion in the via hole may fail in the process in which wiring layers are piled up using a build-up method or the like, and thereby defective printed wiring boards may be produced.
For this reason, each of a via land formed in respective upper and lower wiring layers and a via hole formed in an insulation layer between the wiring layers has been provided with a dimensional allowance for deformation due to external forces arising from temperature hysteresis, humidity hysteresis, polishing, positioning, transferring, and other process conditions. A recent advanced printed wiring board has, for example, a via land of the diameter size 250 μm with respect to a via hole of the diameter size 75 μm.
Like this, the diameter size of a via land is need to be three times or more than that of a via hole, and because much of the space of a wiring layer has to be allocated to the via land, a pitch between adjacent pattern lines formed on the wiring layer are not to be made narrow. That is, known methods for manufacturing a printed circuit board have a problem that the increasing of wiring density is limited.
Incidentally, there is a fact that electronic parts such as IC or the like mounted on a printed wiring board are not subjected to a change in the outer dimensions or the pitch of electrodes even though the printed wiring board itself is deformed. Predetermined dimensions in the area for mounting electronic parts and the pitch of the bonding lands connected with the electrodes should be ensured regardless of deformation of the printed wiring board.